TTL flip-flop with clamping diode for eliminating race conditions

ABSTRACT

A master slave flip-flop includes a data gate for receiving the input data and generating therefrom first and second internal data signals, and a master section for latching the internal data signals and for transmitting such signals to a slave section during predetermined portions of a clock signal. In order to render the internal data signals symmetrical with respect to each other and therefore substantially reduce the possibility of transmitting incorrect data to the slave as a result of a race condition in the master section, a Schottky diode is coupled within the data gate to complete a discharge path for one of the internal data lines and thus prevent it from exceeding a predetermined voltage.

BACKGROUND OF THE INVENTION

This invention relates generally to master-slave flip-flops and, moreparticularly, to a master-slave flip-flop having an improved data gatefor substantially reducing the possibility of transmitting incorrectdata to the slave section due to a race condition in the master sectionwithout sacrificing performance speed.

A well known master-slave transistor comprises a data gate having a datainput (D_(in)) for generating internal data signals (D and D), a mastersection for receiving D and D and a clock signal (C_(p)) and generatingin response thereto first and second signals (A and B) indicative ofD_(in), and a slave section responsive to A and B for storing the inputdata and generating the traditional Q and Q outputs. Unfortunately, thisflip-flop suffers from several disadvantages. The internal data line orsignal D when high is permitted to rise from approximately 2 volts tovery near the supply voltage level (typically 5 volts) while D when highrises to only approximately 2.4 volts. This large voltage swing on theinternal data line D may produce an adverse race condition in the mastersection which results in the transmission of incorrect data to the slavesection. Furthermore, the high maximum voltage attainable at D causes ahigh voltage swing which in turn increases the propogation delays andset-up times. Finally, due to the non-symmetric high and low levelsattainable on D and D, there is a substantial skew between the time ittakes to set a "0" (T_(set0)) and the time it takes to set a "1"(T_(set1)).

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improvedmaster-slave flip-flop.

It is a further object of the invention to provide an improved data gatefor a master-slave flip-flop.

It is a still further object of the invention to provide a master-slaveflip-flop including circuitry for reducing unwanted race conditions inthe master section without reducing speed of operation.

Yet another object of the invention is to provide an improvedmaster-slave flip-flop wherein the signals appearing on the internaldata lines are symmetrical with respect to each other.

According to a broad aspect of the invention there is provided amaster-slave flip-flop, comprising: data gate circuit means forreceiving input data and for generating therefrom first and secondcomplementary internal data signals representative of said input data;master circuit means coupled to said data gate circuit means forreceiving a clock signal and for latching said internal data signalsduring a predetermined portion of said clock signals; slave circuitmeans coupled to said master circuit means for storing said internaldata signals; and means for clamping at least one of said internal datasignals to prevent said at least one of said internal data signals fromexceeding a predetermined voltage so as to render said first and secondinternal data signal symmetrical with respect to each other.

According to a further aspect of the invention there is provided animproved master-slave flip-flop having an output which follows datapresent at a data input and of the type which includes a master sectionresponsive to a clock signal for receiving internal data signalsrepresentative of the input data and a slave section for storing signalsrepresentative of said input data, the improvement comprising: data gatecircuit means for receiving said input data and for generating therefromfirst and second complementary internal data signals representative ofsaid input data; and means for clamping at least one of said internaldata signals to prevent it from exceeding a predetermined voltage so asto render said first and second internal data signals symmetrical withrespect to each other.

BRIEF DESCRIPTION OF THE DRAWINGS

The above, and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the drawing which is a schematicdiagram of the inventive flip-flop.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The flip-flop shown on the drawing comprises a data gate for receivingthe input data signal (D_(in)) and for generating internal data signalsD and D on internal data lines 4 and 6 respectively, a master sectionfor receiving a clock pulse C_(p) at terminal 8 and responsive to D andD for generating signals A and B which, when the clock signal is low,correspond logically to Q and Q appearing at output terminals 10 and 12respectively, and a slave portion 14 for storing the logic signalsappearing at A and B when the clock pulse at C_(p) goes low and forgenerating the traditional Q and Q outputs. The clock pulse C_(p) mustbegin in its high state (a logical 1) in order to recognize changes inthe input data (D_(in)). The data is latched at A and B on the trailingedge of the clock pulse.

The data gate includes Schottky transistors T₅ and T₆, Schottky diodesS₁, S₂, S₃, S₄, and S₅, diode D₁ and resistors R₃ and R₄. Schottky diodeS₄ has its anode coupled to the base of transistor T₆ and a cathodecoupled to input terminal 2. Resistor R₄ is coupled between a source ofsupply voltage V_(CC) and the junction of the anode of S₄ and the baseof T₆. The emitters of transistors T₅ and T₆ are coupled together and,via the series combination of Schottky diode S₅ and diode D₁, to ground.The collector of transistor T₆ is coupled to the cathode of Schottkydiode S₂, to the base of transistor T₅ and to the cathode of Schottkydiode S₃. Resistor R₃ is coupled between V_(CC) and the base oftransistor T₅. Finally, the collector of transistor T₅ is coupled to theanode of Schottky diode S₃ and the cathode of Schottky diode S₁.

The flip-flop's master section includes Schottky transistors T₁, T₂, T₃,and T₄ and resistors R₁ and R₂. The emitters of transistors T₂ and T₃are coupled together and to terminal 8 for receiving the clock signalC_(p). The base of transistor T₂ is coupled to the collector oftransistor T₁ and to the anode of Schottky diode S₁. The base oftransistor T₃ is coupled to the collector of transistor T₄ and to theanode of Schottky diode S₂. The emitter of transistor T₁ and thecollector of transistor T₃ are coupled to node 16, and the collector oftransistor T₂ and the emitter of transistor T₄ are coupled to node 18.The above described signals A and B appear at nodes 16 and 18respectively. Finally resistors R₁ and R₂ are coupled between V_(CC) andthe base electrode of transistors T₁ and T₄ respectively.

To illustrate how the problems described above arise, it will be assumedthat Schottky diode S₃ is not in the circuit. Furthermore, throughoutthe following description, a logical high and a logical low will berepresented by "1" and "0" respectively. Furthermore, it will benecessary to describe voltage levels appearing at various points in thecircuit under certain conditions of D_(in) and C_(p). Thus, the voltageappearing across a standard diode or the base-emitter of any of thetransistors will be referred to as .0.. The voltage across a Schottkydiode will be represented by $ and the voltage drop across a transistorin saturation will be represented by "SAT".

Assume first that Q is "0", D_(in) is "1" and C_(p) is "1". Current willflow through resistor R₄ turning transistor T₆ on. The voltage at thecollector of transistor T₆ will then be approximately .0.+$+SAT. Since.0. is approximately 0.7 volts, $ is approximately 0.5 volts and SAT isapproximately 0.2 volts, the voltage at the collector of transistor T₆may be considered to be 2.0.. Therefore, the voltage of the internaldata signal D appearing on line 6 will be 2.0.+$. Since the base oftransistor T₅ is at a voltage 2.0., it remains off. The voltage ofinternal data signal D appearing on line 4 will be V_(CC) -$. The "-$"term which appears in the voltage equation at D is due to the Schottkyclamp which appears across all of the transistors shown in the drawing.

With D equal to V_(CC) -$ and D equal to 2.0.+$, D may be consideredhigh and D considered low.

When C_(p) begins to go low (i.e. on the trailing edge of the clockpulse), the base of transistor T₂ is at a higher voltage than the baseof transistor T₃. Thus, transistor T₂ turns on first pulling node 18down and turning on transistor T₄. This in turn prevents transistor T₃from turning on. Thus, A may be considered to be a logical high while Bis at a logical low. This information is passed into the slave sectionresulting in a high Q and a low Q.

Clock pulse at C_(p) is permitted to go all the way down to a SAT leveland once there, changes in D_(in) will not effect the state oftransistors T₂ or T₃. When the clock pulse C_(p) again goes high,transistors T₂ and T₃ are turned off, the data which was at A and B whenC_(p) was low is now stored in the slave, and A and B rise to a highlevel.

If now the data input signal were to go low (D_(in) =0), transistor T₆would turn off and current would flow via resistor R₃ into the base oftransistor T₅ turning it on and thereafter, via Schottky diode S₅ anddiode D₁, to ground. Now, the voltage at the collector of transistor T₆equals the voltage at the base of transistor T₅ (2.0.+$). Thus, D equals2.0.+2$. The voltage at the collector of transistor T₅ equals 2.0. andtherefore D equals 2.0.+$.

It can now be seen that D may switch from a low level of 2.0.+$ to ahigher level of V_(CC) -$ while D switches from a low level of 2.0.+$ toa high level of 2.0.+2$. Clearly the switching characteristics of D andD are non-symmetrical with respect to each other.

When C_(p) falls, the base of transistor T₃ is higher than the base oftransistor T₂. Therefore, T₃ turns on causing its collector (node 16) togo low which turns on transistor T₁ latching transistor T₂ off. Thus, Aand Q go low, and B and Q go high.

The problem with this arrangement is that with D charged up to V_(CC) -$and D to 2.0.+$, a condition is imposed on A and B which, with a verysmall differential voltage between the bases of transistors T₂ and T₃,can result in an undesirable race condition. The problem may beillustrated as follows. The status of the circuit is: D_(in) is "0", Qis "0" and C_(p) is again "1". When C_(p) now goes to "0", the voltageat the base of transistor T₆ is $, transistor T₆ turns off, the voltageat D is 2.0.+2$, and the voltage at D is 2.0.+$. The clock signal C_(p)is a low (is at a SAT), the base of transistor T₃ is at .0.+SAT, andnode 16 is at 2 SAT since transistor T₃ is on. The base of transistor T₁is at .0.+2 SAT and the base of transistor T₂ is at 3 SAT. Thus, thebase of transistor T₂ is below its threshold and therefore transistor T₂remains off. The base of transistor T₄ is at .0.+SAT+$ which isequivalent to 2.0.. Node 18 is connected to a transistor in the slave(not shown) the base of which is at 2.0.+$. Therefore, node 18 (and B)is at .0.+$. Thus, there is a differential voltage between A and B (i.e.nodes 16 and 18 respectively).

When the clock signals C_(p) again goes high, transistor T₂ and T₃ turnoff. The voltage at the base of T₁ becomes 2.0.+2$, and the voltage atthe base of T₄ becomes 2.0.+3$. The voltage at node 16 (A) becomes.0.+2$, and the voltage at node 18 (B) becomes .0.+3$. Thus, A and B areseparated only by a $. Since the base of transistor T₃ is higher thanthat of transistor T₂, T₃ should turn on faster when C_(p) again goeslow. This is enhanced since the collector of T₃ is at a lower voltagethan that of T₂ and therefore T₃ has a built-in advantage in the raceagainst transistor T₂. It should be clear by now that in the racebetween transistors T₂ and T₃, in general, the transistor having thehigher voltage at its base and the lower voltage on its collector willturn on first and latch the input data.

The problem manifests itself when the input voltage D_(in) now changes.With D_(in) equal to a "1", transistor T₆ turns on, and transistor T₅turns off. The clock pulse voltage is high (at V_(CC)), D is at 2.0.+$,D is at V_(CC) -$, node 16 (A) is at V_(CC) -.0., and node 18 (B) is at.0.+2$. If the input data should now change to a 0 (D_(in) =0), Dbecomes 2.0.+2$, node 18 (B) becomes .0.+3$, D becomes 2.0.+$, but A(node 16) does not change. It stays at V_(CC) -.0. since there is no wayto discharge it. If the clock pulse C_(p) should now go low, thecollector voltage of transistor T₃ is substantially higher than that ofT₂, and even though transistor T₃ may turn on first, it has to pull itscollector all the way down from V_(CC) -$ and therefore may lose therace with transistor T₂ resulting in incorrect data being stored in theslave section.

This problem in addition to others described previously is solved byadding Schottky diode S₃. Now when the input data (D_(in)) becomes high,and transistors T₆ and T₅ turn on and off respectively, the voltage at Dcannot charge any higher than 2.0.+2$. Not only does this prevent thevoltage at node 16 from being substantially greater than the voltage atnode 18 as described previously, but now the signals appearing at D andD are symmetrical. That is, when D is high it is at 2.0.+2$ and when lowit is at 2.0.+$. Similarly, when D is high it is at 2.0.+2$ and when lowit is at 2.0.+$. Not only has the possibility of an unwanted racecondition been substantially eliminated without increasing propogationdelay or setup time, but the added symmetry has also substantiallyeliminated the skew between between T_(set0) and T_(set1).

The above description is given by way of example only. Changes in formand details may be made by one skilled in the art without departing fromthe scope of the invention.

I claim:
 1. A TTL flip-flop, comprising:data gate circuit means forreceiving input data and for generating therefrom first and secondcomplementary internal data signals representative of said input data;master circuit means coupled to said data gate circuit means forreceiving a clock signal and for latching said internal data signalsduring a predetermined portion of said clock signal; slave circuit meanscoupled to said master circuit means for storing said internal datasignals; and means for clamping at least one of said internal datasignals to prevent said at least one of said internal data signals fromexceeding a predetermined voltage so as to render said first and secondinternal data signal symmetrical with respect to each other.
 2. Aflip-flop according to claim 1 wherein said means for clamping comprisesdiode means for completing a discharge path for said at least one ofsaid internal data signals.
 3. A flip-flop according to claim 2 whereinsaid data gate circuit means comprises:a first transistor having a baseelectrode for receiving said input data, a collector for receiving saidfirst internal data signal and an emitter for receiving a first sourceof supply voltage; and a second transistor having a base coupled to thecollector of said first transistor, a collector for receiving saidsecond internal data signal and an emitter for receiving said firstsource of supply voltage, the base of said second transistor and thecollector of said first transistor for receiving a second source ofsupply voltage, said diode means having an anode coupled to thecollector of said first transistor and a cathode coupled to the base ofsaid second transistor and to the collector of said first transistor. 4.A flip-flop according to claim 3 wherein said diode means is a Schottkydiode.
 5. An improved TTL flip-flop having an output which follows datapresent at a data input and of the type which includes a master sectionresponsive to a clock signal for receiving internal data signalsrepresentative of the input data and a slave section for storing signalsrepresentative of said input data, the improvement comprising:data gatecircuit means for receiving said input data and for generating therefromfirst and second complementary internal data signals representative ofsaid input data; and means for clamping at least one of said internaldata signals to prevent it from exceeding a predetermined voltage so asto render said first and second internal data signals symmetrical withrespect to each other.
 6. An improved flip-flop according to claim 5wherein said means comprises diode means for completing a discharge pathfor said at least one internal data signal.
 7. An improved flip-flopaccording to claim 6 wherein said diode means is a Schottky diode.